1. Field of the Invention
The invention relates to a method of plasma etching and, more particularly, to a method of etching silicon using gas mixtures comprising fluorine (F), oxygen (O), carbon (C), and hydrogen (H).
2. Description of the Background Art
Trenches formed in semiconductor substrates have many uses in producing integrated circuits including isolation, capacitor formation, transistor formation, and the like. One important use of trenches is in the formation of a trench capacitor as a storage node for a dynamic random access memory (DRAM) device. Trench capacitors are desirable because they occupy a relatively small area, while having large electrode surface area due to the depth of the trench used to form the capacitor. In a conventional trench capacitor, the trench walls form one electrode of the capacitor, the walls are coated with a thin dielectric material and then the remaining trench is filled with polysilicon such that the polysilicon forms the second electrode of the capacitor. As such, trench-based DRAM devices utilize less area than other forms of memory devices that use planar or stacked capacitors. To maximize the capacitance of the trench capacitor, the surface area of the trench walls is maximized, i.e., the trench is deep and the walls are substantially vertical.
Traditionally, storage nodes are formed using an anisotropic chemical or reactive ion etching of a masked silicon substrate. Etching chemistries utilize combinations of such chemicals as hydrogen bromide (HBr), chlorine (Cl2), oxygen (O2), nitrogen fluoride (NF3), sulfur hexafluoride (SF6), and nitrogen (N2). For example, an HBr/Cl2 chemistry can provide a silicon etch rate of about 5000 xc3x85/min. with a photoresist selectivity (defined as the ratio of the etch rate of silicon to that of photoresist) of between 3:1 to 4:1. Other material layers such as oxide or nitride can also be used as an etch mask to improve the silicon to mask selectivity. To improve the throughput for wafer processing, it is desirable to maximize the silicon etch rate, especially for applications such as trench etching. In general, however, an increase in the silicon etch rate also decreases the mask etch selectivity.
Therefore, a need exists in the art for a silicon etching method that increases the silicon etch rate while enhancing mask selectivity.
The disadvantages associated with the prior art are overcome by the present invention of a method of silicon etching using a plasma generated from a gas (or gas mixture) comprising fluorine (F), oxygen (O), carbon (C) and hydrogen (H) elements. In one preferred embodiment, an etch gas (or mixture) comprising sulfur hexafluoride (SF6), difluoromethane (CH2F2), and oxygen (O2) is disclosed for trench etching in a silicon substrate at gas flow rates of about 65 sccm SF6, 25 sccm CH2F2 and 60 sccm O2, at a total pressure of about 15 mtorr and a substrate bias power of about 25 W. A silicon etch rate exceeding 1 xcexcm/min. can be achieved with a hardmask etch selectivity greater than about 20:1. In particular, high aspect ratio silicon trenches with submicron dimensions have been etched at a rate of about 1.2-1.5 xcexcm/min., with a hardmask selectivity as high as 28.
The invention can be practiced using, for example, a combination of about 10-100 sccm of a fluorinated gas (i.e., a gas comprising the fluorine element), 1-100 sccm of a fluoro-hydrocarbon gas (i.e., a gas comprising F, H, and C elements), and about 10-100 sccm of an oxygen-containing gas (i.e., a gas comprising the oxygen element), with a total pressure of about 4-100 mtorr. Alternatively, gas compositions comprising SF6:CH2F2 and O2:CH2F2 ratios of between 1.5:1 to 3:1 have been used for anisotropic etching of silicon, resulting in trenches with near-vertical profiles. A decoupled plasma source (DPS) etch reactor is used in one embodiment of the present invention. In general, an inductive source power of about 300-5000 W can be used for plasma generation, with a cathode bias power of about 10-500 W applied to a wafer support pedestal, which can be maintained within a temperature range of about xe2x88x9240 to 60 degrees Celsius.
The etch process of the present invention can also be adapted to etch other forms of silicon material layers, including polysilicon and amorphous silicon, along with the use of a photoresist mask in lieu of a hardmask.